Monday is the set launch date for AMD’s Barcelona CPU Architecture, branded K10.

AMD is prepared to launch its next-generation Barcelona CPU architecture this Monday. Barcelona is the first K8-based product to feature a substantial amount of architectural changes since the original launch of AMD?s Opteron and Athlon 64 processors. Substantial architectural changes aside, Barcelona features evolutionary enhancements to the existing K8.

Barcelona is the company?s first quad-core CPU architecture and features a native quad-core design. Intel?s previously released Clovertown, Kentsfield and upcoming Harpertown and Yorkfield quad-core processors feature two Core-architecture dies on a single package ? effectively quad-core, however, not a native design like Barcelona.

Features include:

• Includes L3 cache which allows all cores to share an additional 2MB of extra cache memory.
• Independent memory controller and the “Memory Optimizer Technology”
• Independent Dynamic Core Technology allows each CPU core to run at a different clock rate. The voltage of the cores, however, is shared and it will be the voltage required by the core that is running at the higher clock rate.
• CoolCore Technology allows the CPU to automatically turn off parts of the CPU that are not being used. Processors based on Core microarchitecture have also a similar feature (?Advanced Power Gating?)
• Dual Dynamic Power Management (DDPM), informally known as ?split-plane?, this technology allows the CPU and the memory controller (which is embedded inside the CPU) to use different power sources ? i.e. voltages.
• Desktop CPUs will use HyperTransport 3.0 instead of HyperTransport 1.x (server CPUs will adopt HT3 only in the future)

Expected K10 server cores:

• Barcelona: quad- or dual-core Opteron on the 2000 and 8000 series, 512 KB L2 memory cache per core, 2 MB L3 memory cache, registered DDR2 memory, socket 1207 (socket F), HyperTransport 1.x, 65 nm manufacturing process.
• Budapest: dual-core Opteron on the 1000 series, 512 KB L2 memory cache per core, 2 MB L3 memory cache, conventional DDR2 memory, socket 1207 (socket F), HyperTransport 1.x or 3.0, 65 nm manufacturing process.
• Shanghai: quad- or dual-core Opteron on the 2000 and 8000 series, 512 KB L2 memory cache per core, 6 MB L3 memory cache, registered DDR2 memory, socket 1207 (socket F), HyperTransport 1.x, 45 nm manufacturing process.
• Montreal: octal- or quad-core Opteron on the 2000 and 8000 series, 1 MB L2 memory cache per core, 6 MB or 12 MB L3 memory cache, registered DDR3 memory, socket G3, HyperTransport 1.x, 45 nm manufacturing process.
• Suzuka: quad- or dual-core Opteron on the 1000 series, 512 KB L2 memory cache per core, 6 MB L3 memory cache, conventional DDR3 memory, socket AM3, HyperTransport 3.0, 45 nm manufacturing process.

Expected K10 desktop cores:

• Spica: A single-core Sempron LE CPU, with 512 KB L2 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
• Rana: Dual-core Athlon X2 LS CPU, with 512 KB L2 memory cache per core, L3 memory cache (value not disclaimed) regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
• Kuma: Dual-core Phenom X2 CPU, with 512 KB L2 memory cache per core, 2 MB L3 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
• Agena: Quad-core Phenom X4 CPU, with 512 KB L2 memory cache per core, 2 MB L3 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
• Agena FX: Quad-core Phenom FX CPU, with 512 KB L2 memory cache per core, 2 MB L3 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+ or socket 1207+.

You can read a more detailed specs and features of the Barcelona from DailyTech.